1. Field of the Invention
The present invention relates to a pixel of an organic electroluminescent display (ELD), in particular to structures of a high voltage device and a low voltage device using steps of silicon element regions in a silicon-on-insulator (SOI) and a method for manufacturing the same.
2. Description of the Prior Art
FIG. 1 is a cross sectional view for explaining structures of a high voltage device and a low voltage device in accordance with the prior art. The high voltage device used for pixels of an inorganic ELD has been manufactured by using the SOI substrate having a silicon element region with relatively thin thickness in order to obtain low junction capacitance. Referring to FIG. 1, the structure of the high voltage device and the low voltage device used for pixels of the inorganic ELD in accordance with the prior art consists of p-wells 114 and 118, a drift region 116, gate oxidation films 126 and 128, gate electrodes 130a and 130b, source/drain regions 136a, 136b, 136c, and 136d, and source/drain electrodes 140a, 140b, 142a, and 142b on a lower substrate 100 and a buried oxidation film 102 of the SOI substrate.
In the high voltage device and the low voltage device in accordance with the prior art as shown in FIG. 1, the junction depth of source regions 136a and 136c and drain regions 136b and 136d is equal to a thickness of an upper silicon layer, which is an active layer of the SOI substrate. In particular, when the SOI substrate having thin silicon element region of 1 μm class (hereinafter, thin SOI substrate) is used, a LDMOS (lateral double diffused MOS) device with low junction capacitance can be manufactured. However, when the thin SOI substrate is used, it has been difficult to control electrical characteristics of the low voltage device by a kink effect, which means a drain current increases drastically as a gate voltage increases in the case of the partially depleted low voltage device applied to logic drive circuits owing to the thin silicon element region. In addition, in terms of the process, it is difficult to manufacture both the low voltage device and the high voltage device compatible with the conventional process of submicron CMOS device at the same time, while adjusting the junction depth between the source and the drain.